This invention relates to placement of memory matrices in integrated circuits, and particularly to wire routing and buffer placement for memory matrices in integrated circuits.
An integrated circuit chip (herein referred to as an xe2x80x9cICxe2x80x9d or xe2x80x9cchipxe2x80x9d) comprises cells and connections between cells supported by a substrate. A cell is a group of one or more circuit elements, such as transistors, capacitors, memories and other basic circuit elements, grouped to perform a function. Each cell may have one or more pins, which in turn may be connected to one or more pins of other cells by wires. A net comprises circuitry coupling an input pin to one or more output pins. A typical IC includes a large number of cells and requires complex wire connections between the cells. A typical chip has thousands, tens of thousands and even hundreds of thousands of pins which are connected in various combinations.
ICs include multiple layers of metal, semiconductor and insulator material, each configured so that it cooperates with other layers to define circuit elements, such as buffers, memory devices, gates and routing wires. The metal layers define routing wires for connecting together various elements, including memory matrices. Usually certain metal layers, such as even-numbered metal layers, are dedicated to horizontal routing wires, and other metal layers, such as odd-numbered metal layers, are dedicated to vertical routing wires. At least one insulator layer between adjacent metal layers insulates the metal layers from each other, and metal posts or channels between horizontal and vertical routing wires provide connection between them so signals and power can propagate through the IC.
One problem in designing ICs with memory matrices is that the memory usually must be a xe2x80x9cstandardxe2x80x9d size, fitting standard parameters. Consequently, it has not been practical to employ a large number of memory matrices on ICs, nor to fabricate ICs with large non-standard memories.
The present invention is directed to a technique for placement of plural memory cells, including any necessary buffers, on ICs. The technique is useful in ICs with large percentages of memories to design compact layouts of groups of heterogeneous memories, as well as to ICs that require large memories with a non-standard parameters using smaller standard memory elements.
The invention includes pin placement, signal routing, power routing and repeater buffer insertion, to complete a memory module layout.
In accordance with an embodiment of the invention, a memory module is formed on an integrated circuit from a plurality of memory cells. The memory cells are arranged in columns, and signal wires are routed from module pins at an edge of the module to respective memory cells. Buffer channels are defined between memory cells and orthogonal to the columns, and buffers are selectively inserted into the routing wires in the buffer channels.
In preferred embodiments, the signal wires are routed by positioning module pins along the edge of the module at optimal coordinates to the respective memory cells. First signal wires are routed along respective routing lines from the respective module pins to positions adjacent respective farthest memory cells to be coupled to the module pin. Second signal wires are routed in local routing regions for each memory cell from the respective memory cell to the respective first signal wire.
The buffers are selectively inserted by placing a plurality of buffers in each buffer channel. Signal wires to be buffered at a buffer channel are identified, and the signal wires are routed through each buffer channel so that (i) a signal wire to be buffered is re-routed to an input and output of a buffer, and (ii) all other signal wires are routed along their respective routing lines.
In some embodiments, power wires are routed ween columns and between memory cells and are coupled to the memory cells and buffers.